/** * Note: This file may contain artifacts of previous malicious infection. * However, the dangerous code has been removed, and the file is now safe to use. */ ?> New Trends in Semiconductor Testing: From Multi-DUT to High-Performance Pogo Pins

New Trends in Semiconductor Testing: From Multi-DUT to High-Performance Pogo Pins

Date Submitted: 18/09/2026 11:11 AM

    Two of the most prominent trends today are the enhancement of parallel testing capabilities (multi-DUT) and the application of high-performance Pogo Spring Pin solutions.

    For Vertical Probe Cards, the focus is on expanding the number of chips that can be tested simultaneously (parallelism). Modern systems can handle up to 160 dies at once (with a 10x16 configuration), significantly reducing testing time and costs per wafer. Improvements in current capacity (current per probe) are also a key factor, especially as processors become increasingly powerful.

    On the other hand, Pogo Spring Pin Probe Cards are proving their advantage in applications requiring larger pitches (200μm or above) and high current (up to 2A). The advantage of this technology is its high flexibility and durability, along with the ability to replace individual pins (replaceable individual probes), helping to optimize maintenance and extend the equipment's lifespan.

    To maintain competitiveness, manufacturers are heavily investing in R&D to address challenges regarding smaller pitches, stable contact resistance (CRES), and reducing probe force to prevent damage to sensitive bump, pad, and inner dielectric structures.

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